Principal / Senior IC Design Engineer

You’ll take digital IP and SoC blocks from concept through to silicon, owning the micro-architecture and RTL implementation across the full ASIC design flow. You’ll:

1. Develop and implement micro-architecture for complex digital blocks
2. Write clean, synthesizable RTL in Verilog or SystemVerilog for a range of IPs and SoCs
3. Run linting, clock domain crossing (CDC) checks, and low-power verification (UPF/CPF)
4. Handle logic synthesis, generate timing constraints, and support timing closure
5. Work closely with verification engineers to shape test plans and uphold design quality
6. Support both pre-silicon validation and post-silicon bring-up and debug
7. Produce and maintain clear technical documentation throughout the design cycle

1. 1. A Bachelor’s or Master’s degree in Electrical/Electronic Engineering or a related field
   2. Solid, proven experience across the ASIC design flow and methodologies
   3. Strong RTL coding skills in Verilog or SystemVerilog
   4. Hands-on experience with synthesis and timing analysis, plus scripting ability (TCL, Python)
   5. Exposure to low-power design techniques and power integrity considerations is a plus
   6. Familiarity with industry-standard EDA tools from vendors such as Synopsys, Cadence, or Siemens
   7. Strong problem-solving instincts and a genuinely team-oriented approach
   8. Clear communication skills and comfort working across a dynamic, global team

EAPersonnel Registration No: R1106329

EA LicenseNo: 12C6254